The Circuit Design And Optimization Of SoC's High Performance SRAM

All kinds of memory will be embedded in today's SoC system in order to improve the system's performance, especially the static random access memory (SRAM). It will be the chief factor when we think about how to select the memory because SRAM is compatible to the standard CMOS process. These memory possess the great proportion of the whole chipset both in the energy consumption and in the chipset area, so the chipset performance is decided by these memory performance. The high performance memory design is most important for SoC system.SRAM circuits need have lower energy consumption, fast access time and little chipset area as soon as possible in SoC system. But by analysis we can see clearly that when we improve one aspect of the circuit performance , the other aspect of the performance will be decreased. So we need to evaluate the change trend of all performance parameter, then we can optimize the design project.Analyzing from the structure of SRAM circuit, we particularly introduce the work state of SRAM's sub-circuit. By using simulation and analytical based characterization model, we make the SRAM's energy consumption model, access time model and chipset area model. After this model is applied to the circuit design of ARM720T's SRAM, we put forward the most optimized design project. At last using this model, we design the Cache which has the 8KB capacity.The 8KB SRAM circuit has been optimized from the circuit structure in this article. We introduce two ways to improve the circuit performance which are lower voltage bitline swing(LVBS) technique and address transition detection(ATD) technique. The LVBS technique is implemented by improving the structure of pre-charge circuit which can decrease the bitline swing of un-hitting memory cell. Then the power consumption will be decreased. ATD technique improve the structure of decode circuit. Using the address transition detection pulse signal, we decrease the open time of wordline and decrease the bitline swing of hitting memory cell.The SRAM which has 8KB capacity is implemented by way of full custom design. The front-end schematic simulation and back-end layout simulation under chart 0.25um process and SMIC 0.18um is passed. Under chart 0.25um process, chipset area of this circuit is 1.92 mm2, access time is 1.8ns, read power consumption is 16.4mW and write power consumption is 13.3mW. Under SMIC 0.18um process, chipset area of this circuit is 1.38 mm2, access time is 1.7ns, read power consumption is 7.5mW and write power consumption is 6.25mW. All of the performance parameter is satisfied by the circuit design. In this article by analyzing the performance model of SRAM circuit, we can find that the partition of the circuit and the sub-circuit is so important for the capacity fixed SRAM circuit. If we divide too many sub-circuit, the chipset area will be larger, otherwise the access time will be longer and energy consumption will be large. So it's very important to use the proper decoding project. After improving the circuit by LVBS technique, we decrease 30 percent's energy consumption both of read and write operation. And 40 percent's energy consumption of read operation is decreased according to ATD technique. Both of the two techniques greatly improved the performance of the SRAM circuit.