Design And Verification Of Memory Control Model Based On High Performance Network Processor

In recent years, with the increases of network scale and the interface velocity, the traditional network devices based on the general purpose processor or ASIC chip can not meet the needs of the processing requirements of the linear speed processing protocol. On the other hand, network communication protocol and standard change rapidly and users’demands rise ceaselessly, which require data communication product to be upgraded quickly. Network Processor (NP) emerges as the needs of this background, its appearance is not only to solve the low performance of the general purpose processor, but also to prove NP has higher flexibility than ASIC. NP can better adapt to the rapid development of data communication industry. The network processor as a typical multi-processor system on chip (MPSoC), which accesses to memory frequently, needs higher requirements of memory access.Based on the network processor of XDNP project needs, this paper focuses on the research of an efficient shared memory access control module for multi-processor system. To relieve the pressure of memory access caused by MPSoC, hierarchical arbitration strategy is adopted by the memory control module, which is the combination of fixed priority algorithm and improved rotation priority algorithm. Fixed priority algorithm considers enough of priority, improved rotation priority algorithm ensures fairness of the memory access and the possibility of continuous read/write commands. Pin module as the most important part in design, this paper adopts instruction prefetch technology combined with instruction cache structure which can achieve address of read/write instruction transmission in pipeline.Finally, this paper completes the functional simulation and implementation on the FPGA platform. As the result shows, the memory control module can complete the SSRAM access for multi-processor. The result confirms the correctness of the design.