Research On High Performance And Low Power Embedded Two-port SRAM

Static random-access memory(SRAM)plays an important role in portable mobile electronic devices,wearable electronic devices,systems on chip(SOC)and other embedded products.With the continuous development of chip manufacturing technology,the performance indicators of embedded chips,such as bandwidth,power consumption,area and speed,are increasingly stringent.Fin FET technology has gradually replaced the traditional planar CMOS technology and has become the mainstream chip manufacturing technology.In order to meet the current design requirements of embedded chips,it is of great theoretical and practical significance to further study the design of embedded SRAM under Fin FET process.In this thesis,the design method of high-performance and low-power embedded SRAM are studied and the main design schemes of dual port SRAM reported at home and abroad are analyzed.Aiming at the problems existing in the existing design schemes,a feasible high-performance and low-power embedded Two-port SRAM is proposed in the research.In TSMC 7nm Fin FET process,the circuit and layout design of a 32-kb,256 bit data width,1-read/1-write Two-port SRAM(1R1W 2P-SRAM)are completed.The main work and achievements are as follows:1.According to the research situation of dual port SRAM,a scheme of embedded Two-port SRAM based on single port 6T SRAM cell is proposed.Compared with traditional dual port SRAM,the overall design has higher density,better read and write performance and lower power consumption.2.Adding the replication array and designing the tracking and self-timing circuit of read and write operation,the write-after-read timing is realized for the Two-port SRAM.The speed and stability of SRAM read operation are improved by designing the voltage latch sense amplifier(VLSA)self-timing control circuit.In order to reduce the word line power consumption and improve the stability of SRAM reading and writing,the high-performance and low-power word line decoding and driving circuit is designed.3.The design of each module circuit of the target SRAM and functional simulation verification,parasitic parameter extraction of circuit layout,post simulation verification,working frequency analysis and power consumption analysis have been completed by using Virtuoso,Finesim and other EDA tools.Finally,the layout area of the proposed Two-port SRAM chip is about 4125.96?m~2,which can save at least 30%of the total area compared with the 8T cell under the same process.Through simulation analysis,the working frequency of the Two-port SRAM can reach 2.5GHz under the working environment of voltage 0.9 V and temperature 100?.In terms of power consumption,the leakage power consumption reaches 8.9?W under the working environment of voltage 0.75 V and temperature 25?.In the dynamic power consumption,the write power consumption is about 10.7m W/GHz,the read power consumption is about13.92 m W/GHz,and the read-write power consumption is about 17.31 m W/GHz.In terms of access speed,the maximum reading time is less than 500 ps at voltage 0.65 V.From the analysis of the overall simulation results,the design goals of the high performance and low power Two-port SRAM have been achieved.