The Research And Implementation Of A 65nm High-Performance SRAM

Static Random Memory (SRAM) as one kind of critical memory is widely used to high-performance microprocessor caches and System-on-Chips (SoCs). Each new technology generation can improve the performance of VLSI chips efficiently, as a result, the design of a high-performance SRAM is highly desirable to satisfy the development. Based on this reason, a 16kB dual-ports high-stability, high-speed and low-power SRAM is proposed by this paper in 65nm technology.In this paper VTC butterfly curve, wordline voltage, bitline voltage and N curve current techniques is introduced to do the static noise margin analysis for 6T cell and 8T cell, and we reseach some techniques on increasing the stability of cell, such as adaptive read/write voltage, negative bitline voltage, dynamic wordline voltage and dual threshold cell. As the simulation shown, 8T cell have a higher SNM than 6T cell, and a smaller cell area and a lower leakage power consumption in the next technology generation.We also adopted dynamic decoder and hierarchical bitline to speed up access and lower power. Three techniques are proposed in this paper to improve reliability. They are separate technique, compensation technique and delay technique which improves the wordline error rates and the reability of dynamic decoder. And hierarchical bitline who is comprised of local bitline and global bitline reduce access time from 690ps to 471ps and lower power from 5.3mW to 3.5mW.To obtain an experimental result, we carried out the simulations with hspice. Compared with the conventional 6T SRAM, the data output delay and power of 8T SRAM reduce by 36.3% and 42.7%, respectively, and cell's read SNM increases by 1600% when supply voltage is 0.8v, although the area has overhead 40.3%...