UHF RFID Reader Digital Baseband Processing SoC Design Based On OR1200

With the development of integrated circuit manufacturing technology, improvement ofautomation level of design tools and elevation of integrated circuit design methodology，the functionof single-chip integrated circuit are getting more and more complex. The migration from ASIC(Application specific integrated circuit) to SoC (System on Chip) is becoming an obvious trend. Thesystem level integrated circuits have the benefits of reduced overall system power consumption, chiparea, and enhanced the speed of chip and the functionality of system. Thus, nowadays SoC designbased on IP (Intellectual Property) cores has become an essential area in very large scale integratedcircuit design.RFID (Radio Frequency Identification) reader is an important part of EPC (Electronic ProductCode) system network. With the advantages of far identifying distance, high transmission speed,convenient operation, multi-target recognition, moving object recognition etc, Ultrahigh FrequencyRFID becomes more and more popular. Currently, most of the radio frequency identification products,especially hand-held RFID devices are designed in UHF band. Being used in an increasingly widerapplication range, as well as the improvement of IC technology, readers of RFID, especially thedigital baseband signal processing part would see the inevitable trend of being integrated into a singlechip. Therefore, research on this area which is the topic of this thesis has great practical significance.This thesis designed the SoC of digital signal processing baseband of RFID readers complyingwith ISO18000-6C. OR1200, Wishbone, GPIO, UART16550and debugging IP Cores maintained byOpen Cores organization are used in the design. Baseband processing IP core has been developed bythe author. In addition, some IP cores such as on-chip RAM, PLL were obtained by Quartus II IP coregeneration tool. Wishbone bus has been used as the system bus, which is supported by OpenRISC.System design procedure started with system, then to modules. Analysis of the principles and featuresof custom-designed IP cores, design of baseband signal processing IP core and IP coresinterconnection are the main task of hardware design. GNU tool chains have been used as thesoftware development platform. The bootloader and testing files were coded using C language.Finally Modelsim is used to simulate and GDB is used to debug the software and finish systemverification on FPGA.