FPGA Design And Realization Of UHF Passive RFID Reader

Radio Frequency Identification (RFID) is one of the automatic identification technologies which can achieve intercommunication by using wireless channel .it can be used to trace and manage each kind of goods object, compared with the low frequency system, 860MHz~960MHz RFID system has father reading distance and faster read ect. Nowadays, it has become a hot spot in RFID research.Base on ISO/IEC 18000 Type B protocol, a kind of RFID reader with Ultra High frequency (915MHz) is designed in this thesis. Firstly, the thesis analyzes the principle of RFID system and the ISO/IEC 18000-6 Type B protocol shortly. Subsequently, puts forward a circuit design scheme for RFID reader base on cooperative work of FPGA and mcu, and the RF transceiver module and the antenna module are designed simply. Finally, design and realize the digital logic system of reader deeply. firstly, Overall analyze and partition the digital logic system; secondly, it designs the circuit of five sub modules, including data sending, data receiving, host controller, clock divider and communication interface in RTL level, also simulates and verifies their functions; thirdly, the testbench for the digital logic system is designed and the whole module is simulated using ModelSim software, The result shows that the designed in this thesis has met the need of the protocol; fourth, the logic synthesis and timing analysis are implemented on the digital logic system in Quartus II software with FPGA Cyclone serial chip EP1C6Q240C8 of Altera company, the result shows that the digital logic system fulfills the timing request.