| Following computer and Internet, IoT (Internet of Things) as the third informationreform wave in the world, has attracted extensive attention and study from governmentsall of the world, high-tech enterprises and their technological workers. Among the threelayers of the IoT, the perception layer is especially important, which bears the task ofcollecting information, and one of whose key technologies is RF identification. SinceUHF RFID network reader device has long identification distance, fast read and writespeeds, network data transmission and other advantages, it has wide applicationprospect and economic value. Therefore, it is of great applicative value to make anindependent research and develop a high performance ultra-high network reader.Firstly, we analyze the UHF RFID protocol of ISO/IEC18000-6C in detail andintroduce the command set, the code, the decoding rules, and the internal logical storagestructure of the tag. According to the requirements of protocol parameters modulationmode, and considering the difficulty of radio frequency demodulation, a RF receiverreception circuit implementation scheme of UHF network reader is being presented. Thedesign structure of the scheme is reasonable and feasible, with low cost and goodquality. The main control chip FPGA configures the carrier chip Si4133G-BT to receivethe carrier signal through SPI bus format data, and to realize the digital frequencymodulation for eliminating the blind spot problem encountered in reading tags. The chipof RF switch HMC195modulates the pulse interval encoding data, which amplified bythe RF2376former driver, and outputted by the RF2173power amplifier. The RFreceiver adopts multi-channel zero-IF demodulation to receive scheme, and gets thedigital waveform using high-speed comparator MAX942ESA.Secondly, we design the PC software, which uses VC++6.0software customframes format, and designs most of the set of commands in practical application toreach to interact with the user.Moreover, we use Verilog language and the up-down design method in the digitallogic system of the reader. From theory to specific interface and to the internal registersdefinition, as well as to the conversion of data flow. We have carefully designed the UART module, the PC command decoding module, the PC respond-to-reader module,the main control module, the reader command package module, tag informationdecoding module and the network communication module.Finally, we tested each indicator of the system and the virtual serial ports ofsoftware, and done a Modelsim simulation to the implementation of digital logic RTL,and sampled and analyzed internal embedded logic analyzer data. The test of thefunctions of hardware and software of the whole system shows that the UHF networkreader reaches the expected designed requirements. |
