Built-in self-test methodologies for concurrent testing of analog/mixed-signal systems-on-chip

The increasing level of integration of circuits into a single semiconductor die is one of the most challenging aspects of design and test engineering. The benefit of integration into a system-on-chip (SOC) is increased functionality and reduced cost per function, but at risk of ever increasing test costs. With analog/mixed-signal (AMS) test becoming the dominant factor of test costs, still at the present time the majority of analog circuits are tested using expensive but limited-throughput analog testers. Limitations of automated test equipment (ATE) are starting to incur longer manufacturing test times associated with testing mixed-signal integrated circuits.;ITRS raises concerns related to escalating cost of test, and places focus on reduction of time-to-market and increase of multisite/concurrent testing as means to reduce the cost. This dissertation responds to aforementioned concerns with a framework that reduces dependency on ATE resources, improves observability, improves concurrent test capabilities and enables embedded execution of high performance tests.;At the fundamental level, three basic phenomena are measured: voltage, current and time. Every test associated with an AMS circuit-under-test (CUT) can be mapped into voltage, current or time measurement. This work's primary concern is measurement component of test, and there are multiple indications of how to expand it to stimulus component of test as well. The central theme is time-based embedded test instrumentation (TBETI) which fundamentally manipulates time variable to perform embedded testing. Three major components of VITAL (V=voltage, I=current, T=time, AL=analog) sensing are covered with emphasis on analog/mixed-signal power system-on-chip.;The principal contribution is the voltage instrument capable of making concurrent voltage measurements in the low-frequency and DC regime. Instrument uses pulse-width modulation technique to convey voltage information from sensor to test core. Distributed and scalable architecture supports high levels of concurrent measurement acquisition. A novel way of compression of pulse-width modulated analog information is proposed, which reduces bus size between peripherals (sensors) and the core, making it highly distributed. The architecture offsets exceptional opportunities to trade-off test time and resolution when needed, and optional built-in feature which seamlessly integrates into the existing framework.;Number of high current tests on analog/mixed-signal power system-on-chip is significant to the point it is becoming the bottle neck. Adding large power device for test purposes is not feasible, so "recycling" approach is proposed. Both linear and switch-mode regulators contain idle power devices which can be utilized for test purposes and reduce dependency on automatic test equipment (ATE) resources. Measurements of critical current parameters are performed in co-test configuration with ATE, while at the same time dynamic characteristics are evaluated in a concurrent fashion.;Since the instrument core uses time as intermediate variable, inherently it can measure time directly. New generation switch-mode regulators need tight timing control, so burden to measure very short delays is present. Proposed scheme discretizes an incoming pulse and locks it in a ring oscillator. Once the signal is repetitive, the time amplification is utilized to bring the signal into the range suitable for measurement with existing instrumentation.;A balance of design-for-test (DFT) methodologies, such as on-chip instruments, and ATE instruments must be obtained to perform testing in most efficient and effective manner. On-chip instruments capable of sensing fundamental parameters (such as voltage, current and time) are deployed throughout the SOC. Such sensors are capable, in a concurrent fashion, of taking a "snap-shot" of the device under test (DUT) while easing access to embedded circuits. Embedded VITAL (voltage-current-time-analog) test network alleviates constraints related to ATE throughput while being an enabling block for true AMS built-in self-test (BIST).