Research On Low Power Test Technology And Temperature Aware Test Scheduling For System-on-Chip

In recent years, SoC (System-on-Chip) has become the mainstream of current researches and applications in the integrated circuits. With the increase of integration scale and design complexity , test is facing great challenges. Numbers of cores embedded in SoCs, the limited I/O port resources, the cost of external test equipment, and the limitation of data path lead to the increase of design complexity and test cost. BIST (Bulit-in Self-Test) is capable of testing the circuit through the integrated additional logic, which is an effective solution for embedded core test in SoC.During test, the power consumption in circuits is several times higher compared to the normal function. The excessive test power will endanger, even damage the test circuit. SoC test power has become the focus of the test researchers. Reducing test power of SoC can be considered from core level as well as the system level.In this paper, the vector generation for low power test of chip-level BIST, and temperature aware test plan for SoC have been investigated, including:(1) Research on seeds selection algorithm of low power SIC test sequences. In SIC test sequences there is only one single bit reverse, which can reduce the toggle rate of the internal nodes in CUT. Seed selection of SIC test sequences is the key of BIST vector generation technique. In this paper, the character of the SIC sequences is proposed on the basis of the early theoretical model, which is used as a guidance in designing the seed selection algorithm of SIC sequences. There is usually a problem of coverage in the seed selection of SIC sequences. Two kinds of selection algorithm of SIC sequences seed selection have been proposed in which the SIC seed vector is extracted based on ATPG test pattern collection. The SIC test sequences generated in the seed release can reduce the test power of CUT, as well as guarantee the same high fault coverage with the ATPG tools. Firstly, a new kind of SIC sequences, called SSIC (Sequential Single Input Change) sequences is proposed and its character is intensively studied and summarized, which is used in the seed selection algorithm of SSIC sequences. The hardware of the SSIC sequences generator is based on simple shift register. Another architecture of SIC sequences generator is based on primitive polynomial LFSR, in which single input change in the sequences is carried out according to the order of M sequence generated by LFSR. Different initial value of LFSR leads to different SIC sequences generated by the same SIC seed, as a result of which the initial value of LFSR is co-considered in SIC sequences seed selection to optimize the number of the seed.(2) Utilizing CA as the built-in vector generator in is the deterministic BIST is the problem of CA reverse synthesis, a difficult in which is the existence of the large amount of evolutionary characteristics violations. In this paper the asymmetric nearest-neighbor model suitable for CA is defined and the capability of dealing with evolutionary characteristics violations is further improved. Usually the deterministic BIST test technique is based on reseeding, and the storage of the seeds needs extra hardware overhead and a large amount of unwanted vectors released will increase the time and cost of test. Two kinds of low power deterministic TPG synthesis algorithm have been proposed, introducing the asymmetric nearest-neighbor model to deal with evolutionary characteristics violations. Both of the two algorithms utilize ATPG vector set through low power pre-computation to do reverse synthesis. The CA structures synthesized are able to generate low power test set, maintaining the same high coverage with ATPG tools and short test time. One of the two algorithms uses neighborhood expansion combined with line exchange technique, and in order to minimize the hardware cost of CA structure SA algorithm is utilized and the threshold of the neighborhood radius is set to constrain the connection topology among the CA cells. In the other algorithm the numerical matrix model of nearest-neighbor is derived from the variation law of the three-neighbor and asymmetric three-neighbor of the center cell in CA. Through computation the nearest cell connection structure that satisfies the evolutionary characteristics is obtained. If there is no solution to the current neighborhood radius, the radius is increased incrementally, and then the new three-neighbor matrix is calculated until the optimized connection structure is found out. This method can reduce the hardware overhead of CA, as well as improve the algorithm efficiency. The proposed deterministic TPG synthesis algorithm based on CA focus on the manipulation of the low power vector set, which will not affect the low power character of the original vector set and coverage. Given the initial vectors of CA, the pre-computation low power test vector set is generated using low power TPG synthesized based on CA, and there will be no redundant vectors, which will solve the problem of time and power overhead caused by the redundant vectors in the reseeding technique.(3) The system-level temperature aware test plan technique has been investigated. Research of SoC temperature aware test plan mainly include two aspects: one is planning algorithm design and the other temperature assessment of system test that is also the basis of all. In this paper a temperature assessment based on numerical heat transfer theory is proposed. The placement of cores under parallel test can be inferred according to the spatial distribution and the defined neighborhood matrix. The heat transferred among the cores is calculated based on the model and then the summation of the heat and the source is the temperature. This method could solve the problem of the complicated temperature assessment caused by repeatedly calling the heat simulation tools and the requirement of multiple establishment of heat transfer path in the common RC heat model. The system test temperature can be fast estimated by the proposed model. A temperature optimized SoC test plan using GA (Genetic Algorithm) is proposed based on the temperature assessment model. Two kinds of chromosome coding scheme are defined taking the plan and temperature assessment into account. The chromosome is coded and decoded in different stages and one point crossover at the boundary of the segments and swap variation within the segments are applied, which can deal with the invalid solutions in the GA application and temperature aware test plan. The proposed scheme can minimize the system test time and guarantee the thermo safe test. By defining the sum of the temperature fitnesses of all the cores under test as the total fitness, the test plan for heat balance distribution of the entire chip can be obtained.