Comparator Design Based On 0.18μm CMOS Technology

Analog/digital converter -A/D converter has been widely used in radar, satellite positioning, and a variety of electronic components. Recognized industry A/D converter is a fully parallel architecture, and in the A/D converter, especially in the flash memory structure, the comparator in which play a crucial role as a key unit. To meet the speed requirements for the comparator to latch comparator for the structure of most ultra-high-speed comparator emerged.In this paper, TSMC 0.18μmCMOS technology as the basis, design and simulation of a pipelined ADC is suitable for high-speed comparators. The pre-amplification uses regenerative comparator latching structure is composed of three subunits:a preamplifier, the latch comparator output amplification stage. This design using Cadence simulation software for design and simulation, the simulation showed that:at 1.8V operating voltage, enabling the transmission delay 90.5ps, the maximum error of ±5mV high-speed comparators. Finally, Cadence simulation software comparator layout design, the layout area is 0.0072mm2, and passed the DRC and LVS verification.