Design And Research Of Ultra-high-Speed Analog-to-Digital Converter

Data converters,including analog-to-digital converters(ADCs)and digital-to-analog converters(DACs),are key modules in mixed signal processing systems.In recent years,with the development of digital signal processing technology,radar technology and wireless network communication technology,the speed of signal processing is faster and faster,and the performance requirements of ADC are also higher and higher.Research on ultra-high-speed ADC technology has great significance in wireless network communication,radar,optical communication,aerospace and other fields.Firstly,this thesis introduces the basic principle of ADC circuit and the definition and calculation methods of various static and dynamic characteristics,and also introduces various structures of ADC circuit.For the ultra-high-speed design requirements of 10 GSps,the ultra-high-speed ADC based on 0.13 μ m SiGe BiCMOS process is designed with full parallel structure,and the key circuit modules of the fully parallel structure ADC: track-and-hold amplifier,comparator and decoder are implemented deeply..In the research of ultra-high-speed track-and-hold amplifier(THA,Track-and-Hold Amplifier),the THA circuit in this thesis adopts fully differential structure,which effectively suppresses common-mode noise and reduces the influence of even harmonic components on the circuit.The input buffer module effectively suppresses the non-linearity of THA circuit by using diode-connected transistors.At the same time,the input buffer module adopts the structure of emitter follower,which effectively reduces the output impedance and provides greater driving current for the following module.The output buffer module uses capacitance enhancement technology and emitter coupling technology to improve the analog input bandwidth and dynamic performance of THA.In the research of ultra-high-speed comparator,the ultra-high-speed comparator in this thesis is composed of preamplifier circuit and latch circuit.The preamplifier circuit consists of two-stage amplifier circuit.The Gilbert cell structure adopted in the first stage amplifier circuit makes the comparator combine well with the differential input signal and the differential reference level of the front stage,mainly providing wide bandwidth;the second stage amplifier circuit mainly provides high gain.The latch circuit adopts a positive feedback emitter-coupled-logic(ECL)circuit structure,which effectively improves the working speed of the comparator and the driving ability of the latter circuit.In the research of ultra-high-speed decoder,the ultra-high-speed decoder in this thesis adopts fully differential circuit structure,which effectively suppresses the common-mode noise interference.At the same time,an innovative ROM-based decoder is designed,which reduces the sensitivity of the decoder to noise,reduces the error rate of the decoder and improves the working speed of the decoder.On the basis of the above research,this thesis completes the design of 3-bit 10-GSps full parallel ADC circuit based on SiGe BiCMOS technology.The simulation results show that the maximum sampling rate of the ADC is 10 GSps,and the absolute values of differential non-linearity and integral non-linearity are less than 0.2LSB,the ENOB is 2.5bit,and the power consumption is1.6W.The post-simulation results show that the absolute value of differential non-linearity is less than 0.83 LSB,the absolute value of integral non-linearity is less than 1.5LSB,the ENOB is 1.8bit.and the power consumption is 1.9W.Therefore,the ultra-high-speed ADC circuit designed in this thesis can be applied to the systems such as electronic countermeasures and radio astronomy.