System Model And Calibration Technology For High Precision Pipelined A/D Converter

Pipelined A/D converter has both the advantages of high sample rate and highprecision. Nowadays the most popular pipelined A/D converters’ sample rate can reacha few tens to a few hundreds of millions hertz and the conversion precision will hitabout10bits. Hence this type of data converter is widely utilized in wirelesscommunication, radar remote sensing and high precision graph process systems. Withthe specific sample rate and power consumption, the pipelined ADC find hard toimprove the precision due to the inevitable deviation in silicon manufacture process.For that reason, we need to ask digital circuits for assistance to compensate oreliminate the non-ideal effects in analog circuits under the acknowledgement thatdigital designs is simpler, faster, more simple to implement and less power and chiparea cost.In this thesis, a system model of13bits pipelined A/D converter is built with theconfiguration of2.5bits for the first stage following nine stages of1.5bits/stagestructure and one two-bits Flash ADC. The non-ideal effects considered in the thesisinclude capacitor mismatch, comparator threshold offset, opamp limit open loop gainand its nonlinear gain. Based on this original non-ideal system model, two digitalcalibration models are built applying the algorithm named lease mean square rootapproximation running in foreground and background respectively. The digitalcalibration models extracting the error information in the system aim at adjustingsystem original outputs to its expected values.Two digital calibration models are simulated and verified in Matlab. Comparisonof the effective and performance of two models is drawn. In the foreground model,working beyond ADC normal operation period, a high precision DAC is added togenerate the given test signals, which accelerates the convergence rate. On the otherhand, the background model simultaneously working with ADC, utilized an extra set ofcomparators in the calibrated pipelined stage for calibration coefficients extraction.The simulation result shows that in the foreground working mode the SFDR, SNDRand ENOB improve from47.3dB,43.2dB and6.9bits to76.7dB,70.1dB and11.2bits.While in the background working mode, LMS can improve the ENOB to11.4bits.Both the kind of working modes can effectively improve the system linearity.According to different applications, we can choose the proper working mode to calibrate the pipelined A/D converter.