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Automatic Current Switching Control PLL Circuit Design

Posted on:2015-02-21Degree:MasterType:Thesis
Country:ChinaCandidate:Z L SunFull Text:PDF
GTID:2268330428972607Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
Phase-locked loop (PLL), widely used in the frequency synthesizer, which is an important module of mixed-signal circuits. Because of its inherent self-healing, PLL is a beneficial tool to achieve the reliability and stability of integrated system, such as the central processing unit, clock and data recovery, and signal modulation in the telecommunications system. The inherent self-calibration frequency characteristics of PLL make itself to be one of the most important modules in a number of the chip.This paper starts with the basic principle of PLL system, introduces a system-level linear model and instructive for PLL circuit; then describes the frequently-used PPL:CPPLL, introduces its basic structure and composition of the module. Based on the above basis, the PLL circuit designed in this paper which controlled and switched by an automatic current, the loop bandwidth will be more self-adaptive, it also solves the problem of bandwidth will be smaller while improving the stability of the loop. It will be very instructive for the research of low noise, and fast locking PLL in future.this paper processes system-level modeling, module design and system simulation, then tests and verifies the feasibility and reliability of this systemTemperature at-40o C to+90o C, the craft corner is tt, ff, ss, supply voltage2.7V to5.5V, emulate the overall performance with cadence spectre:Lock time is25us; Consumption is862.4u A; output frequency is27.12MHz; phase noise is98.9dBc/Hz@100KHz. The CP-PLL designed in this paper will get a target with variable bandwidth and high stability though the result of simulation.At the end, this paper processes the schematic and layout design and silicon-proven, then does the frequency stability testing and phase noise testing after packaging the Tape-out, measured results: When-40o C to+90o C and the supply voltage is2.7V to5.5V, the lock time is400us to500us, phase noise is-83.05dBC/Hz@100kHz to-90.02dBC/Hz@100kHz, measured results has deviation from the design results, As for the practicality of any action, the test results meet the expected design goals.
Keywords/Search Tags:Phase Locked Loop, Wide Power, Adaptive, Bandwidth Control, LowPhase Noise
PDF Full Text Request
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