Research And Design Of An Adaptive-bandwidth High-order All Digital Phase Locked-loop

The adaptive-bandwidth phase locked-loop can resolve the contradiction between loop's bandwidth and noise perfectly, compared with the traditional phase locked-loop of fixed bandwidth. Now adaptive-bandwidth phase locked-loop implemented by analog circuit was comparatively complex, furthermore, analog elements in the loop circuit were prone to disturb by environment, so the whole locked-loop's performance was influenced. The adaptive-bandwidth all digital phase locked-loop implemented by all digital circuit, its circuit structure was simple, ability of resisted noises was stronger, stability was higher, use was wider, and it's not only was made single integrated phase locked-loop, but also was able to as a function of module embedded to a system of chip(SOC),constituted the on chip phase locked-loop.Compared with the second-order phase locked-loop, Performances of the high-order phase locked-loop at the phase error of steady state, the time of locked, the frequency of pulled range, and the spur suppression were excelled to the second-order phase locked loop. The high-order phase locked-loop at high requirement situation has a broad application foreground.In this paper, based on the theoretical analysis of the phase locked-loop, used a second-order filter based on the proportion- integral (PI) controlled algorithm as the third-order phase locked-loop's filter. We started from establishment of the third-order analog phase locked-loop's continuous domain model, combined with the phase locked-loop to achieve adaptive-bandwidth criteria, using the method of bilinear transformation, which is the best precise method of mapping a analog phase locked-loop to a digital phase locked-loop, established a discrete domain mathematic model of the adaptive-bandwidth high-order all digital phase locked-loop. Analyzed the system's stability using the high-order systems theory and the theory of high-order closed-loop dominant poles. Derived the formulas calculated parameters of the adaptive-bandwidth high-order all digital phase locked-loop, completed the designed circuit of adaptive controlled module with EDA technology and the method of top to down, the adaptive-bandwidth high-order all digital phase locked-loop using the module can adjust its bandwidth and system parameters automatically with the change of its input signal, so that the phase locked-loop has the best performance. Using the method of building DSP builder model completed the basic phase locked-loop circuit, in the research domain of all digital phase locked-loop, the method was a relatively new design method, which only allowed designers to focus on building the module of the system level, without writing complex code. The designed adaptive-bandwidth high-order all digital phase locked-loop was simulated under the environment of Matlab/simulink and Quartus II. Implemented the designed phase locked-loop in FPGA and tested the hardware, based on the software simulation was right.Software simulation and hardware test results were consistent with that: the designed adaptive-bandwidth high-order all digital phase locked-loop not only had a large locked range, fast locked time, well stability, but also had a good tracking performance when the input signal was a frequency step or ramp signal.