Development And Performance Evaluation Of Low-phase-noise High-stability Fast-locking Phase-locked Loop

The phase-locked loop(PLL)can track and lock the phase of the reference input signal and is a classic closed-loop negative feedback control system.Phase-locked loops are widely used in communications,power systems,precision measurement and automation.Compared with the analog phase-locked loop,the digital phase-locked loop has the characteristics of easy integration,stable parameters and strong anti-interference ability.The analog phase-locked loop has problems such as low phase detection accuracy,nonlinear voltage-controlled oscillator,and easy saturation of various components.These problems have been solved in the digital phase-locked loop.Therefore,the digital phaselocked loop has been greatly developed.Traditional digital phase-locked loops can only track simple digital signals,which only have two states of 0 and 1.The new digital phase-locked loop designed in this paper can track complex analog signals The phase-locked loop adopts a new structure that combines proportional-integral control and active disturbance rejection control.When the output signal has delay interference and phase noise,the system can eliminate the influence of both.On the problem of phase detection deviation caused by output signal DC offset or burr signal,this paper improves the traditional frequency and phase detection device to eliminate the phase detection deviation.In addition,this paper also designs an adaptive controller,which has the functions of frequency preset and parameter adaptive control.The frequency preset makes the numerical control oscillator in the phase-locked loop work directly near the center frequency,which greatly reduces the Reduced loop lock time.The traditional digital phase-locked loop control parameters are fixed,and can not balance the phase-locking speed and anti-interference ability.The parameter adaptive control obtains different control parameters according to different reference input signal frequencies and continuously adjusts the control parameters in the process of loop locking,which solves the contradiction between phase locking speed and anti-interference ability.This paper analyzes each module of the loop and the overall mathematical model,and finally uses the Verilog hardware description language to complete the circuit design on FPGA.The clock of the system is 50 MHz.The measured results show that the new digital phase-locked loop designed in this paper has lower phase noise than the traditional digital phase-locked loop.In the case of no delay interference,the digital phase-locked loop can complete the phase lock in one cycle.In the case of delayed interference,the digital phase-locked loop completes phase locking within 3 to 5 cycles.The loop phase locking range is 25 k Hz～5MHz.The absolute value of the phase steady state error is less than 20 ns.The phase-locked loop circuit has the advantages of low phase noise,high stability,fast locking,strong versatility and easy integration.