Enabling techniques for wide bandwidth fractional-N phase locked loops

Delta-sigma fractional-N phase locked loops are widely used for frequency synthesis in electronic communication systems. A wide bandwidth makes it possible for the delta-sigma fractional-N phase locked loop to perform digitally-controlled frequency modulation at high bit-rates, thereby simplifying transceiver circuitry. Wide bandwidth delta-sigma fractional- N phase locked loops offer a multitude of other benefits that contribute to lower costs and a reduced power consumption in the electronic communication products which use these phase locked loops. In spite of the benefits, wide bandwidth delta-sigma fractional-N phase locked loops have not gained general acceptance because of their poor phase noise and spurious tone performance, particularly when they are implemented in integrated circuit (IC) form.; This dissertation presents two signal processing techniques---a phase noise cancellation technique and a charge pump linearization technique---that significantly reduce phase noise and spurious tones in a wide bandwidth delta-sigma fractional-N phase locked loop. Chapter 1 presents a prototype CMOS IC that demonstrates the efficacy of the two techniques---reduction of the phase noise by at least 16 dB, and reduction of spurious tones by at least 8 dB---in a 2.4 GHz delta-sigma fractional-N phase locked loop with 460 kHz wide bandwidth. Chapter 2 presents a theoretical basis for the phase noise cancellation technique and suggests design guidelines to tailor the technique to meet the target requirements of a general wide bandwidth delta-sigma fractional- N phase locked loop. The effectiveness of the phase noise cancellation technique hinges on eliminating limit cycles in the digital delta-sigma modulators, which the technique employs. Chapter 3 presents conditions to theoretically guarantee that one-bit dither eliminates limit cycles in a large class of digital delta-sigma modulators. It also extends the theory to suppress spurious tones in a large class of delta-sigma modulator based digital-to-analog conversion systems.