Circuit Design Of Low Noise Phase-locked Loop

All kinds of wired and wireless communication technologies have developed rapidly in contemporary times.Increasingly high-speed and high-quality communication has put forward stricter requirements for various indexes in the communication system.The phase-locked loop module is widely used in various communication systems due to its frequency tuning ability and easy integration.The phase noise of the phase-locked loop will directly affect the bit error rate and other indexes of the communication system,and the poor phase noise performance cannot be tolerated in high-order modulation methods.In this thesis,the following research is made on how to achieve a low-noise phase-locked loop:1.The structure and characteristics of the traditional phase-locked loop are described,and its transmission characteristics and noise transmission mechanism are analyzed based on the small signal model of the Laplace domain,especially the quantized noise of the fractional phase-locked loop is analyzed.After that,the existing low-noise phase-locked loop structure Sub-sampling phase-locked loop is analyzed in depth,its work and locking process are described in detail,and the phase domain model of each module of the Subsampling phase-locked loop is calculated,and the reason for its good in-band noise performance is obtained.Finally,the stray generation mechanism of the Sub-sampling phase-locked loop is compared with the charge pump phase-locked loop,the influence of the sampling process on the frequency is analyzed,and some solutions are given.2.Analyze the bandwidth limited problem of the existing Type-Ⅱ phase-locked loop,and explain the phase noise of the bandwidth restriction on the phase-locked loop.When the optimal bandwidth of the phase-locked loop is greater than one-tenth of the reference frequency,the noise of the Type-Ⅱ phase-locked loop cannot be optimized by increasing the bandwidth.Based on the existing dual-loop phase-locked loop structure,this thesis adds a Type-Ⅰ Sub-sampling loop with large bandwidth and fast speed to the Type-Ⅱ Subsampling phase-locked loop.The Type-Ⅰ loop does not have a bandwidth limitation of one-tenth of the reference frequency,which can achieve large bandwidth.At the same time,it is analyzed that the bandwidth of the Sub-sampling dual-loop phase-locked loop is mainly dominated by the large-bandwidth loop,so the Sub-sampling dual-loop phaselocked loop suppresses oscillator noise more obviously,and can realize a low-noise integer-N Sub-sampling phase-locked loop.In the end,an Sub-sampling double-loop phase-locked loop with a frequency of 0.8GHz was fabricated under the 28nm CMOS process,with an integral jitter of 1.2ps,which is about lps lower than without adding a class Ⅰ loop,and the power consumption is about 5.2mW.3.The quantization noise in the fractional-N phase-locked loop is reviewed,and it is pointed out that increasing the operating frequency of the delta-sigma modulator can reduce the level of quantization noise.By explaining the shortcomings of the existing logic gate to construct a frequency doubling circuit,a phase-locked loop in the form of a cascade is proposed.The total output noise of the first stage phase-locked loop will directly affect the in-band noise of the second stage phase-locked loop.Therefore,the first stage is used for frequency doubling of the Sub-sampling phase-locked loop,and the second stage uses the charge pump phase-locked loop for fractional frequency doubling to achieve a low-noise fractional phase-locked loop.In the end,a decimal phase-locked loop with a fundamental frequency of 9GHz and a triple frequency output was fabricated in the 28nm CMOS process,with an integral jitter of 380fs and a power consumption of 20.2 mW.