Research And Design Of Ethernet Eye Diagram Test Equipment

With the widespread use of computers, the Internet has been very important to social life.Internet users and network traffic grow at an exponential rate every year. The capacity andcomplexity of network interconnect devices are also increasing at the same time. All of theseput forward higher requirements on the performance of network interconnect devices. How tomeasure and evaluate the performance of network interconnect devices is becoming more andmore important. Currently, the performance tests of network interconnect devices andresearch of related test equipment, are becoming a research hotspot. As a fast and intuitiveevaluation method of network signal quality, eye diagram has been applied in networkconstruction, operation and maintenance procedures. Researchers can analyze the impact ofinter-symbol interference and noise on the signal through eye diagram, to assess the degree ofnetwork merits. Therefore, this paper carries out the research and design of Ethernet eyediagram test equipment, in order to ensure the network operate effectively and stably. Thispaper also provides solutions to diagnose network problems quickly.Firstly, the relevant theories, methods and techniques of existing Ethernet eye diagramtest equipment are in-depth analyzed, and the technical difficulties of Ethernet eye diagramgeneration are summarized, and the domestic and foreign solutions of Ethernet eye diagramtest equipment are further analyzed.Secondly, the advantages and disadvantages of PLL-based CDR, and clock and datarecovery method based on oversampling are analyzed. And full digital clock and datarecovery combing PLL and oversampling is proposed. Using FPGA, each module of the fulldigital clock and data recovery method is designed. Simulation results show that the methodof clock and data recovery effectively reduces the degree of circuit complexity, shorts the locktime and improves the jitter tolerance of system.Again, the scheme of Ethernet eye diagram test equipment based on OMAP-FPGA isproposed, which includes Ethernet eye diagram test interface equipment, signal conditioning,AD acquisition, clock generation, high-speed data storage and pretreatment circuit, powersupply and other circuits. On this basis, signal integrity of Ethernet eye diagram testequipment is analyzed, and solutions to deal with reflection, crosstalk problems of the PCBare proposed.Finally,10M,100M Ethernet signal using principle prototype of Ethernet eye diagramtest equipment developed by laboratory are respectively measured and Comparatively analyzes measurement results provide by Tektronix oscilloscopes with special eye testsoftware. Test results show that the error of eye parameters measured by the designedEthernet eye diagram test equipment was within5%. This paper provides a strong basis andreference for the development of the country Ethernet eye diagram test equipment.