An Ultra Low Power Fault Tolerant SRAM Design

With the increment of mobile, biomedical and space applications, low-power consumption semiconductor digital systems are required. As a main part in digital systems, low-power memories are especially desired.However, the reduced Static Noise Margin (SNM) of Static Random Access Memory (SRAM) in sub-threshold operation imposes great challenges to the sub-threshold SRAM design. The conventional 6-transistor SRAM cell does not function properly at sub-threshold supply voltage range because it has no enough noise margin. In order to achieve ultra low-power at sub-threshold operation, previous research work has demonstrated that the read and write decoupled scheme is a good solution to the reduced SNM problem. To mitigate the single-event effect, improve the stability and also maintain the low power characteristic of sub-threshold SRAM, a Dual Interlocked Storage Cell (DICE) based SRAM cell was proposed to eliminate the drawback of conventional DICE cell during read operation.In this thesis, a 1K×8 bits SRAM test chip was designed, simulated in TSMC 90nm CMOS technology. Simulation results suggest that the operating frequency at VDD = 0.3 V is up to 2.7 MHz with power dissipation 0.35μW, while it is 58.2 MHz at VDD = 1V dissipating 83.22μW. However, the area occupied by a single cell is larger than that by conventional SRAM due to additional transistors used. The main contribution of this thesis project is to propose a new design that can simultaneously solve the ultra low-power and radiation-tolerance problem in large capacity memory design.