Design Of High Read Stability Low Leakage Sram Using Nine-transistor Cell

As the semiconductor technology developing, technique size has continuously been shrinking, and microchips have entered the nanometer era. Therefore, the static power has taken an increased proportion in the entire power consumption。The decreasing in operating voltage as well as the fluctuation in threshold voltage caused by random doping have brought challenge to the read stability issue. Analysis and design of read stability and static power in this paper are based on the 130nm technology.This paper firstly introduces the technology of low static power and stability of write and read process, then gives a fully analysis on the structure, principle and character of the nine-transistor SRAM(static random access memory) cell, explains its advantage in lowering power and upgrading read stability. This paper also compares the new nine-transistor cell to the traditional six-transistor cell and finds twice as much SNM and 20 percent decreased in static power.Then the whole scripture and principle of SRAM is discussed in this paper. The structure of the 8k SRAM and peripheral circuits that is needed is planned out too.This paper designs an 8k SRAM using the nine-transistor cell. It consists of the cell array, precharging circuit, column and row selecting circuit, address decoder, and sense amplifier. This paper also develops the power-saving design of precharging circuit and sense amplifier and proposes a structure of row selecting circuit specially designed for the unique read and write characters of the nine-transistor SRAM cell. Leakage power consumption of the SRAM cell using the nine-transistor cell is about 15 percent lower than that of the one with six-transistor cells. And read access time of it is only about 1.3ns under 100MHz working frequency. The low-power design of the peripheral circuit also apparently reduces total power consumption.