Design And Analysis Of Operational Amplifiers For High-Resolution Pipelined ADC

Operational amplifier is the kernel module of MDAC in pipelined ADC, while the nonideal characteristics of the operational amplifier may have a strong impact on the function of MDAC, and whose functions determine the precision and speed of pipelined ADC.To realize higher gain and wide output swing, two-stage operational amplifiersis achieved in this paper, whose first stage is fulfilled by gain boosted cascode operational amplifier(GBCA), and whose secondstage is fulfilled by simple common source amplifier, and cascode compensation is adopted for frequency compensation. This paper is composed of two aspects as follows:(1) A fully differential, high gain two-stage operational amplifier being applied to the first-stage MDAC circuit of pipelined ADC is designed by the silicon CMOS technology of0.35um/3.3V. In this paper we make the pole-zero analysis aim at two-stage operational amplifier, and make optimize aim at cascode compensation. Pole-zero locationsare analyzed to optimize the circuit structure with the technology of cascode compensation, enables the system phase margin satisfy the stability request to improve the stability by adding a pair of MOSFET in parallel with input tubes. The simulation results show that its DC gain can reach93.77dB, its gain bandwidth is767MHz and its phase margin is30deg, which can meet the requirement of system.(2) A single-stage cascode amplifier with gain boosting technology is designed. Gain boosting technique helps improve the DC gain of cascode operational amplifiers with no change in DC operating points. In this paper, modeling building and numerical simulation for the transfer function of gain boosted cascode amplifiers are presented, which can guide the design of auxiliary operational amplifiers and main operational amplifiers and optimize the settling time of GBCA.The bandwidth and built-up time is optimized in result. The layout design is accomplished based on the silicon CMOS technology of0.35um/3.3V, and the simulation results show that its DC gain is60dB, its gain bandwidth is646MHz and its phase margin is75.7deg.The operational amplifier on chip is measured at last, and the simulation result shows that its DC gain is51.4dB.