Design Of 14bit 150Ms/s Pipelined SAR ADC

High speed and high-precision analog-to-digital converter(ADC)is a necessary circuit to connect analog circuit and digital circuit.Pipelined ADC can cascade many low precision sub ADCs,so the its precision and conversion speed can be very high.However,an amplifier needs to be inserted between two adjacent sub ADCs,so the power consumption is relatively high.Compared with Pipelined ADC,SAR ADC has no amplifier and only one comparator,so its power consumption is relatively low.Because only one digital code can be quantized in each quantization cycle,the conversion speed is medium.Considering the resolution of comparator,the conversion accuracy can not be very high.So the pipelined SAR ADC,which is a mixture of SAR ADC and pipelined ADC,has been paid more and more attention.Through reading the papers,the stage of the designed pipelined SAR ADC is determined to be two stages.Through MATLAB mathematical modeling,the precision of each stage of the sub SAR ADC is obtained from three aspects of power consumption,speed and redundancy range.Finally,a series allocation scheme of 8(1,3)+ 10 is adopted,that is,the precision of the first stage sub ADC is 8 bits with 1 bit intra stage redundancy,the actual precision is 7 bits.There is 3-bit inter stage redundancy between the first stage sub ADC and the second stage sub ADC,and the precision of the second stage sub ADC is 10 bits.In order to further improve the speed of the first stage sub ADC and reserve more time for the residual amplifier to amplify the residual,the 2b/cycle SAR ADC is used as the first stage sub ADC.In order to reduce the layout area of the first stage sub ADC,the structure of the traditional 2b/cycle SAR ADC is improved,that is,the embedded threshold comparator is used to replace the reference DAC which is used to generate the reference voltage for each quantization.In order to avoid the offset correction of the embedded threshold comparator,the embedded threshold comparator mentioned in the paper is improved to enhance the stability of the comparison threshold of the embedded threshold comparator with the change of PVT.As the internal comparator of2b/cycle SAR ADC will have mismatch,this dissertation uses 1-bit internal redundancy with 3-bit inter stage redundancy to solve the problem of mismatch.In this dissertation,this method's principle is analyzed detailedly and the correctness of the method is verified by MATLAB mathematical modeling.The dynamic residual amplifier based on charge sampling is used in the residual amplifier,and the background correction method is used to correct the gain variation with PVT.In this dissertation,the circuit design,construction and layout drawing of 14 bits150MS/s Pipelined SAR ADC are completed in 28 nm process,and the whole circuit is pre simulated and post simulated by HSPICE.When the power supply voltage is 1V,the sampling frequency is 150 MHz,and the input signal frequency is Nyquist frequency.Based on the HSPICE simulation results,Under TT,the spurious free dynamic range(SFDR)of pre and post simulation is 97.037 d B and 94.082 d B respectively,the signal-tonoise ratio(SNR)is 85.832 d B and 82.489 d B respectively,the signal-to-noise distortion ratio(SNDR)is 85.448 d B and 82.105 d B respectively,and the significant bit(ENOB)is13.902 bits and 13.346 bits respectively.