Research On Pipelined ADC Structure And Key Blocks Aiming For Power Optimization

Monolithic integrated ADC has been widely used in many fields such as Wireless Communication, Data Acquisition, etc. With the rapid development in these fields, as the key block of system data procession, ADC has been desired not only high speed and high resolution, but also low power dissipation. How to decrease power dissipation with systemic or circuit design is becoming an increasingly important issue in the design of ADC. In this dissertation, the system structure and key blocks of pipelined ADC are studied and optimized aiming for reducing power dissipation, and then a 3.3V 10-bit 100Msps Si-CMOS pipelined ADC is designed. The main contents are as follows.Firstly, based on the analysis and parameter modeling of system noise limitation and main power blocks, the effects of system parameters on power dissipation of pipelined ADC are deduced and a novel stage-resolutions distribution theory aiming for power optimization is presented. In this theory, a minimum comparator number algorithm (MCNA) is introduced first, and then the optimum distribution of stage-resolutions through pipelined ADC stages is proposed by combining scaling down technology with MCNA. Corresponding to this theory, a system design scheme is established. For 10-bit 100MHz pipelined ADC with scaling down technology, verified by MATLAB and SIMULINK CAD tools, an 8-stage topology with the stage-resolutions distribution (3, 2, 2, 2, 2, 2, 2, 2) achieves the power optimization with 1-bit redundant signed digital correction. Considering the circuit working state and the capacitor mismatch in the process, the 7-stage structure, (3, 2, 2, 2, 2, 2, 2, 2) , is decided finally as the optimal architecture.S/H circuit, comparators, MDAC circuit and sampling switch for Pipelined ADC are studied and optimization schemes are presented correspondingly. New clock feedthrough frequency compensation (CFFC) strategy is presented for the Folded Cascode OTA in the S/H circuit, which reduces settling time by 22.7% without dissipating extra opamp power. Novel preamplifier latch comparator topology reduces comparator power to merely 118μW at a sampling rate of 100MHz, and decreases transfer delay time into 231ps. In the MDAC circuit, not only scaling down technique is utilized from stage to stage for shrinking MDAC power, but both continuous-time and switched-capacitor CMFB are also implemented in the two stages respectively, reducing the load capacitance from the order of pF to 10-2 pF, which saves opamp power that drives load capacitance and ensures high performance of opamp accordingly. CMOS bootstrapped sampling switch with high linearity is employed, which effectively restrains nonlinearity from switch sampling time uncertainty, clock feedthrough and switch charge injection, promoting SFDR to 89dB compared with 58 dB contributed by traditional MOS switch.Based on the layout design principle and rules of Mixed-Signal IC, according to working-state of the designed ADC and practical process circumstance, the layout of 10-bit 100MSPS ADC is designed with standard 3.3V 0.35μm 2P4M Mixed-Signal CMOS process. Total die size of this ADC is 2.5×2.4mm~2 which has 28 pads. Simulated with Cadence simulator after LPE, the results show that under 3.3V supply voltage, this ADC achieves DNL≤±0.2LSB, INL≤±0.49LSB, which are both smaller than typical requirement±0.5LSB. SFDR is 75.06dB at Nyquist frequency. Take process tolerated error into account, an analysis of process corner is accomplished with SS, TT and FF models respectively, and ADC power dissipations are 84mW, 89mW and 98mW correspondingly.