| At present,operational amplifier and its feedback network can be used to realize a variety of mathematical operations and signal processing among input analog signals.The performance of these signal processing circuits mainly depends on the performance of operational amplifiers.It is of great theoretical significance and practical value to study the design method and circuit structure to improve the performance of operational amplifier.Among many indexes used to measure the performance of operational amplifiers,gain and power consumption are the most important.However,they are difficult to achieve at the same time.Therefore,trade-offs should be made according to specific applications.In order to meet the requirements of high-precision ADC/DCA,instrumentation amplifier,audio amplifier and other applications,this paper aims to improve the gain of operational amplifiers and reduce the power consumption of operational amplifier are the main tasks.In this paper,a high gain three-stage operational amplifier has been designed.Five transistor full-differential,telescopic cascode and typical common source were used as amplifier stage,and common mode feedback,frequency compensation and bias circuit were also designed.According to the pole-zero theory and the pole-split effect of operational amplifier,the Nested Miller compensation(NMC)and the Impedance adjustment compensation(IAC)were applied to this operational amplifier.This operational amplifier was designed by the transistor with voltage withstand value of 3.3V in TSMC 0.18?m CMOS process,and was simulated by HSPICE software.When the supply voltage was 3V,the open-loop gain was 155 d B and the unit gain bandwidth was 110 Mhz.With NMC compensation structure,the phase margin was 84° and the static power was 7.07 m W.With IAC compensation structure,the phase margin was 58.3° and the static power was 7.14 m W.In order to improve the gain of operational amplifier under low voltage and low power,a three-stage operational amplifier with low power consumption and high gain has been designed after comparing the current design methods of gain improvement.The first stage was fully differential input stage,the second stage was complementary current mirror load amplifier,which inherits the advantages of high gain of current mirror load and realizes double-ended output.The third stage was common source structure to increase output swing.The self cascode was used to increase output impedance to improve gain.The common mode feedback circuit,frequency compensation circuit and bias circuit were also designed.According to the pole-zero theory and the pole-split effect of operational amplifier,the damping-factor-control frequency compensation(DFCFC)technology was used to compensate the frequency to ensure the stability of the operational amplifier.This operational amplifier was designed by the transistor with voltage withstand value of 1.8V in TSMC 0.18?m CMOS process,and was simulated by HSPICE and Cadence software.When the power supply voltage was 1.8V,the gain was 123 d B,the phase margin was 62°,the unit gain bandwidth was 76 MHz,and the static power was 0.512 m W;when the power supply voltage was 1.3V,the gain was 90.8db,the phase margin was 62.3°,the unit gain bandwidth was 70 MHz,and the static power was 0.176 mw.The simulation results showed,with the self cascode structure and the supply voltage reduced,the power of the operational amplifier was significantly reduced and the gain became higher.These research results provided a reference for the design of low power and high gain operational amplifiers. |
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