Study And Design Of Calibration Techniques For Pipelined ADC Based On Extra Stage

Pipeline ADC which has high speed, high resolution, low power consumption and other characteristics is widely used in high resolution digital image processing, video processing, broadband wireless communications, and other fields. However, with the development of integrated circuits process, the performance of pipelined ADC is facing with huge challenges due to the non-ideal factors such as the finite Op-amp gain, nonlinear error, capacitor mismatch and etc. Thus, digital domain calibration technique has become a hot topic.In this thesis, the impact of linear and nonlinear errors of pipelined ADC and different popular calibration techniques were studied. It is concluded that the main signal path is different from the reference path which would decrease the resolution rate of the pipelined ADC and down sampling of the main signal path would increase the design complexity of the entire system. To solve the unsynchronized problem, a novel calibration scheme was proposed in the new system, the reference ADC was replaced by an accurate extra stage to calibrate the inherent stages without the down sampling module.The key analog integrated circuit modules of the extra stage calibration system such as the switches, two phase non-overlapping clock, comparator, Op-amp, sub-ADC and MDAC were designed based on Cadence Spectre, and the entire calibration system was modeled in Matlab/Simulink. The simulation results showed that the ENOB and SFDR of the 16-bit pipelined ADC with sampling rate of10 MSPS were improved from 9.37-bit and 59.96 d B to 15.32 bit and 99.55 d B after calibration. FPGA verification was implemented by related Cyclone product of Altera Inc., and the spectra analysis showed that the ENOB and SFDR of 16-bit pipelined ADC were 12.73-bit and 98.62 d B after calibration under the input signal with frequency of 4.7605 MHz, which proved that the calibration technique based on extra stage worked well.