Variation Torrent Technology For SRAM Timing Control Circuit

With the ever increasing expansion of the applications in mobile internet where to low power and fast data access is needed, the demand for wide-voltage and low power static random access memory (SRAM) is increased significantly. At the moment, in order to get high performance and low power, advanced process technology and dynamic voltage and frequency scaling (DVFS) are used in mobile internet chips. But due to the progress of the semiconductor process, the process variation also shows up an ever increasing trend, especially at low voltage. This trend of process variation leads to many problems and challenges for the SRAM design and one of the biggest challenges is that the ever increased margin of access operation may cause the performance of the SRAM to be postponed, and this will lead to extra power consumption. As for this issue, the thesis explores the effects caused by the process variation upon the wide-voltage and low power SRAM design and a technique also proposed to tackle the problems caused by the process variation. The main researches are as follows:First, finding the key path of the SRAM, that is timing control circuit And the thesis analyzes the effects on SRAM timing control circuit by process variation at wide-voltage. Then, the thesis discusses some existing timing control circuit techniques, simulating and comparing them at SMTC65nm process technology, pointing out the shortage of each technique.Based on the analysis of above, the thesis provides a new variation-tolerant technique called multiple-stage parallel replica-bitline delay addition technique (MPRDA), and introduces its technology principle, circuit implement and working principle. Based on the analysis of its technology principle, the MPRDA technique can get the optimal discharging time of the bitline by apply the new technique, as a result, reducing the access time and power consumption. In order to verify the effectiveness of the MPRDA technique, a Monte Carlo simulation is taken and an comparison with the proposed techniques. The result shows that the MPRDA technique has the smallest value of timing variation, access time and power consumption, especially at low voltage, e.g. at0.8V, timing variation reduced78%, resulting in21%and13%improvement of the access time and power consumption respectively.