Research On Timing Modeling Of VDSM IC Cells

As VLSI circuit grows larger and the design task becomes more complex, dynamic simulation with circuit simulators for verifying the timing correctness is not practical under deep subjtnacron designs. Now static timing analysis (STA) which is a very powerful technique is used commonly. STA is pattern independent, implicitly verifies all signal propagation paths in the design, and is applicable to very large designs. However, with the trend of narrower IC feature size, timing analysis is a very challenging task and interconnects with RC characteristic is a big challenge to traditional timing models: Firstly, the load of cell is not the capacitance any more because of the RC interconnects. Secondly, the power supply voltage drop is large and should be considered in an accurate and efficient manner during timing analysis. Finally, as device densities increase, interconnect capacitive coupling with a switching net makes the delay on timing path more uncertain. So it is necessary to have good timing models for timing analysis.Nowadays, lots of models have been presented, but these models have some shortages and can't be used widely. For example, the effective capacitance model and effective voltage source model offered in file have lots of calculations and provide pessimistic delay approximation which is unacceptable. And dynamic timing analysis including power supply noise doesn't based on STA and the method of estimation of maximum power supply noise is also pessimistic.Faced with these problems, this file presents a new modified ECSM (Effective Current Source Model) which captures the non-linearity of quasi-capacitive loading by two piecewise-linear approximations after analyzing the traditional timing models. At the same time, this file presents a new timing model considering power supply noise effects. This model keeps the arithmetic of STA based on the effective connection of scalable polynomial with lookup table method. Modeling quality is evaluated both by theoretic and experimental approaches, the result shows that the improved models possesses advantages in terms of accuracy, speed and adaptability to advanced IC technology.