The Embedded SRAM Compiler Design And IP Verification

With the rapid development of semiconductor memories in recent years, SRAM are widely used in various high-speed applications. SRAM only needs long-term power supply instead of refreshing memory cells periodically, it is a kind of static access memory. As a crucial part of high-performance systems in modern processors, SRAM is usually used as a multi-level cache that can bridge the access time gap between processors and DRAM. With the gradual development of embedded SRAM, SRAM is usually embedded as a part of circuit to the SOC chip.Traditional full-custom SRAM design typically requires longer design period, more personnel requirements and higher development costs. Generally, depending on user’s requirement, the size of memory has a wide range in ASIC chip design. How to design SRAM and generate all IP cores quickly and accurately has become a difficult problem faced by designers. However, SRAM compiler is designed to meet the needs of majority frameworks in variable size, and also the software that combines cell library design with automatic program. Pre-built templates and physical cell libraries can simplify the code to write and reduce the complexity of IP cores to generate.Faced with above problems, based on the design and simulation of SRAM circuit, we develop a SRAM Compiler with a range of64B to512K, which automatically generates IP cores according to simulation datasheet, templates and cell libraries. The IP cores contain Lib model, SPICE netlist CDL, GDS layout, etc.Firstly, for the Lib model of28nm process, this part comes up with a Detail Power SRAM circuit architecture, which can analyze the impacts on SRAM power due to the flips of each port. In Detail Power circuits, in consideration of resistance and capacitance of long wires that affect signal transmission, we use π-type structure to model RC of wires and devices connected. According to SPICE netlist and modelling parameters of Detail Power circuits, the power of per SRAM port is obtained by simulation with Hspice. After that, we develop Lib Viewer, a tool with graphical user interface (GUI) to analyze Lib model datas in the form of linear graph.Then, this paper presents the stitching algorithm and the development of analyzation tools for CDL and GDS, including the CDL Viewer with GUI that verifies CDL in the form of tree diagram and the GDS Builder that identifies Smart Option in layout to achieve the modification of GDS and generate Power Ring automatically.At last, this paper realizes the verification of SRAM Compiler IP cores and proposes performance parameters to evaluate the rationality of SRAM design, including Write/Read margin and the critical voltage difference in sense amplifier, etc. Until now, the SRAM Compiler has been transplanted to the SRAM design of180nm,130nm,65nm and40nm process nodes successfully.