An On-chip Circuit For Timing Measurement Of SRAM IP

SRAM is an important module in the SoC and its timing parameters affect the performance of the whole system significantly.However,it is hard for the Electronics Design Auomation(EDA)tools to calculate the timing parameters accurately when the process is unstable.How to obtain the timing parameters of SRAM IP in those unstable processes has become a problem in the industry.This thesis proposes an on-chip circuit to measure the timing parameters of SRAM IP.This circuit can measure the setup time and access time of multiple I/O ports,including both the conditions of rising and falling signals.Digital delay lines are used to generate signals with specific delay times.A calibration scheme is implemented to eliminate the influence of working environment and process variation.Delayed signals are transmitted to each input port by a tree structure module.A signal-edge-convert module is designed for the condition in which the I/O signals are falling signals.A control logic circuit is integrated in the chip and it can automatically execute the testing procedures according to input instructions.Post-layout simulations conducted in CSMC 130 nm technology show that this chip has a measurement ranged of 0?4.8 ns with a resolution of 9.8 ps.Relative measurement error caused by the delay lines is around 3.8% and it decreases with the increase of the measured value.The measurement circuit proposed in this paper has configurable capability and could be applied to the timing measurement of other synchronized circuits.