The Research And Implementation Of JPEG Baseline Mode Encoders Based On FPGA

The rapid development of multi-media technology presents a great challenge for data storage, communication and processing. This thesis makes a research on compression of still images of multi-media. JPEG is a commonly used digital image compression algorithm officially known as ISO/IEC Standard 10918. JPEG has been widely used in multimedia communication for its excellent performance on compressing continouse tone still image.The conception of JPEG baseline mode and the flow of FPGA design are firstly introduced. The traditional architecture of JPEG baseline mode encoder is presented. Disadvantages of traditional architecture are discussed and an enhanced architecture is proposed. Design principle, structures and Verilog implementations of modules in enhancement JPEG baseline mode encoder are described in detail in follow sections. After that, the thesis gived out the detail of each module also with the simulation oscillograms and the implementing results.While designing the system, I spent a lot of time in considering how to divide and define each module and how to coordinate and interconnect these modules. I followed the top-down method to design. First defined the top module, and then divided the top module to several independent small units. In the design of JPEG coder, traditional algorithm on DCT transform is improved, the problem of time parallel is resolved with pipeline optimization algorithm, and the speed of DCT module is accelerated. When I construct the logic, I pay much attention to hardware resource spending and concurrent execution of the Verilog Language to make the design close to the hardware work way, so we could get a high speed with a low hardware spending to satisfy the demand of the cost, performance and practicability.The full design and each module are synthesized in logic, then are simulated in function and timing on Quartus II EDA tool-desk of Altera Corp. The result of synthesis and simulation indicate that the IC design of JPEG image compression based on FPGA can give a better performance on speed and resource using with less hardware resource and a higher frequency, and can meet the requirement of real-time application of JPEG image processing.This thesis investigates the design technologies of complex SoC (System on Chip) by means of designing and implementing JPEG encoder operating in baseline mode. It provides preliminary study for large scale SoC.