A Reaserch Of Phase Locked Loop Design Applying To Universal Serial Bus Equipment

In recent years, because of its convenient features USB technology has been widely used in all kinds of electronic products. Only with a stable system clock, USB device can work efficiently in synchronization and sampling. The conventional USB controller which can provide system clock through the integrated PLL also need an external low-frequency crustal oscillator to work properly. It makes the system clock which provided by the PLL largely dependent on the accuracy of the external crystal, also increasing the cost and complexity of board level circuit.To solve the problem, an implemented method of low power consumption PLL applying to the USB equipment is proposed based on HHNEC0.35μm process. With the basic structure of PLL, we design the clock information extraction unit which can work properly with PFD to fulfill the function of the comparison of the two signals. In order to achieve the compatibility in USB2.0with different transmission rate, Mode switching unit has also been added to the PLL. We also designed the low power control module which can reduce the power consumption of the circuit by shutting down part circuit. What’s more, an improved phase frequency detector, charge pump circuit, voltage controlled oscillator and divider is implemented to the proposed phase locked loop, and the phase locked loop layout is completed.At last, we complete the circuit simulation by Cadence-Spectre. The result shows that the designed PLL can provide low-jitter system clock without an external crystal, and the performance meet the predetermined design target.