Full-custom Design And Implementation Of Multi-port Register File In40nm Process

The number of registerfiles in the new microprocessor becomes more and more.The performance area and power accounted for the proportion of chip. The performanceof register file becomes an important factor that affect the performance of the processor.Therefore, to enhance the performance of the register file becomes the focuses ofcurrent research.This topic aims at the deep research related to the design theory andimplementation techniques of register file, to design and optimize the register file andthe high performance as its main objective, and in40nm CMOS1P9M process toachieve a6reading5write32words of78-bit register file in a full custom method., Thesimulation results show that the layout of the entire register file read "1" delay367ps,compared with the semi-custom, clock frequency has improved52.3%and meet thedesign requirement of2GHz. The main work and contributions are as the followingaspects:1. In the design of the decoding circuit using a new two parity dynamic decodingstructure the parity word line signal, a decoder can be generated by controlling thelowest address bit. This structure allows a50%reduction in the number of the decoder,the static decoding performance improved by25%.2. Using a new storage structure in the design, the coordination of such a structureand control signals can be achieved the read-after-write operation. With this structure,the register file achieved the high performance of the design requirement, and reducesthe complexities of the readout circuit.3. To select the appropriate method of drive unit by estimating the load, to improvethe signal drive problems and delay in the layout.4. To extract the functional model of the register file, LEF physical view and LIBtiming model in the implementation process, and to improve the reusability of registerfile. In addition, the study also researched the scalability of register file, proposed aflexible method of increasing the number of word lines and bit lines, and analysedexperimentally the effect of this method to the delay.The above research result has reduced the delay of register file and is applying toproject.It has accumulated experience for the design of registerfile in40nm process.