Full Custom Design And Realization Of Large-scale Multi-port High Speed Register File

From the born of microprocessor to now, register file as its key part, requires higher read and write access speed. But, along with the development of the register file directing to large-scale and multi-port, realizing a high speed design becomes a difficult problem nowadays.Focusing on a 64-bit high-performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128-word 65-bit general register file with 12-read and 8-write ports which is a representational one for its large-scale and multi-port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. From the layout simulation result, under the 0.18um process, the upper limit working frequency for the register file is 900MHz. In the process of design, the thesis using the circuit structure of inverter series within memory cell, and sharing read and write ports within multi-bit for the first time, solves dominoes effect for driving multi-read port problem, and reduces layout area of double-memory cell for about 40%, respectively.Otherwise, as a memory component, large-scale register file holds a large number of data, so it requires stronger stability and validity. For memory components, using BIST method to make a fault checking is a relatively good choice. But the BIST of the multi-port register file is still in early phase of development. Not only fault model, but also test arithmetic demand to be farther improved.The thesis, focusing on the 20-port register file, makes a fault analysis, particularly in complex bridge fault and crosstalk coupling fault aroused by word-line and bit-line of 20-port. Then, the thesis, based on March C- algorithm, shadow read and shadow write technologies, put forwards BIST arithmetic for the 20-port register file.