Based On The 65 Nm Process Register Pile Design Technology Research

With the development of the fabrication technology and the architecture innovations such as superscalar and VLIW, the operating frequency of processors is increasing very quickly and the processors become much more complex. It is required that the register file (RF) not only has high performance and low power, but also has multiple ports to write and read simultaneously. In addition, the RF is also required to have strong robustness due to the process variation. Furthermore, due to the developments in the field of medical and wireless sensors, the processor is supposed to work at sub threshold voltage to reduce power consumption significantly and it has become a hot research topic to design the sub threshold RF. This thesis focuses mainly on the design of high performance, low power, multi-port RF, and also includes some research of sub threshold RF.We design and tape out32x32b RFs with4read ports and2write ports in65nm CMOS Low Power(LP) technology using full-custom design.Firstly, we do the preliminary research of the RF and propose a new output module that can improve robustness and reduce power. The chip test demonstrates that it can operate at0.8GHz, consuming7.2mW at1.2V. We also design a RF that uses sense amplifier and propose a structure that can regulate the swing on the read bit line.Furthermore, this thesis introduces the improved design based on the results of the first tape out. The new RF with smaller storage cell and new clock controlled world pulse occupies only0.01mm2.The chip test demonstrates that the RF can operate at1.56GHz at1.2V and consume11.8mW. If not including the setup time and hold time, the RF itself can operate in about2GHz.At last section, this thesis researches and designs the RF at the sub threshold. First this thesis analyzes the work status of the CMOS circuits. Then a new storage cell is proposed and new read and writes methodology is adopted based on the working status at sub threshold voltage.