The Design And Implementation Of A 600MHz Multi-port Register File

DSP based on VLIW often issues instructions simultaneously, which needs a multi-port register file for simultaneous access, with high performance, low power and small area as the keys.According to the structure and requirement of XDSP, the technology of multi-port register files is researched. And the contributions are as follows.The optimization of structure and circuitry achieving 625MHz includes the arrangement of register's reading, execution and writing back in different stages shortens critical paths, the utilization of plus clock skew improves the performance as well as reading circuit, push-and-pull write port and two level static decoder that are optimized with the technology of logic effort and obtain 11.1% speedup to reduce access time. The delay is reduced by 27.3% in bypass with low-VT device.A variety of technologies are employed to reduce power dissipation , such as gated clock, multi-VT, reading in reverse, multi-level decoding, switching dynamic signals to static signals and so on. The maximum power consumption is 52mW, smallest among register files with the same scale, only to occur when all ports are working and read ports are reading number 1 at all bits,Basing on the long data's characteristics, port multiplex and detached layout technology are proposed, reducing seven decoders and register cells'ports together with 19% of the area.Further research on register file with even more ports is discussed. The improvement of shared word line leads to the decrease of reading speed by 32.9% and writing speed by 4.9%.Generally, this paper designs a 32-word×32-bit 13-read, 9-write ported register file in 0.13μm, in which read operations is followed by write operations in the same cycle. Whenever the read address is identical to the write address,the write data is forwarded by bypass. The register file is taped out in XDSP, and works well in 625MHz.