Full Custom Design And Implementation Of High-speed Register File Of X Processor In 65nm Technology

As the processor's frequency is on the rise, the bottleneck of performance has shifted to the storage components and I/Os. Register File is a key part in microprocessor, located in the top level of memory hierarchy, so it requires the highest access speed. The X microprocessor is a 64-bit multicore multithreading high-performance microprocessor, and is also an excellent floating-point processor. As a key point of the whole design, the Floating-point Register File needs high frequency, large scale and multi-port. Considering the speed of half-custom design based on standard cell is hard to satisfy the requests, the full-costom design method is chosen.The FRF ( floating-point register file ) has been implemented in 65nm CMOS process. It has 2-read and 2-write ports, supporting multi-theading. The size is 256-word×78-bit. The simulation results indicate: the read delay is 383ps, the write delay is 287ps, and the clock frequency is up to 2GHz. Comparing with the synthesis result of half-custom design, the clock frequency increased from 1GHz to 2GHz, which is optimized nearly 1 times, and the area reduced from 732857μm2 to less than 400000μm2, which is optimized nearly 45%, and the power is also improved by the application of Power-Gating. They all achieve the design aim.The thesis mostly aims at high speed and low power. The main factors which affect the Register File's speed have been optimized, and Low-power design techniques have also been applied:1. Combining with the RF's larger capacity and characteristic of supporting multi-threading, it adopts the strategy of selecting after the 8-threading's reading out parallel which reduces the delay of the key path and the total power effectively.2. Since the RF has 256 words, it adopts the decoding structure with two parallel stages to achieve 8-256 decoding, which can enhance the speed of reading and writing decoder, thus improving the performance of the entire circuit.3. Adopting the fast and dynamic address-comparing circuit to solve the problem of conflict between read and write, only writing operations response when the same floating-point register file is being read and write.4. Using Power-Gating technology in this memory, the whole circuit can reduce 59% standby power and 12% active power to achieve the design goals of low power consumption.