Full-custom Design And Implementation Of Multi-port Register File

Register file, as the hottest functional part, has a direct impact on the performance of the microprocessor. A large multi-ported register file is indispensable with great development of modern computer architecture. In this paper, we use the full-custom method which reduces the area, access time, and energy consumption of the register file.The main work and contribution is as follows.1. We optimize a 600MHz 32×32-bit 13-read, 9-write register file in 0.13μm CMOS technology. Based on the theory of logic effort, we optimize the decode cell. The structure change of memory array into read-write-apart brings in the convenience of verification. To meet the demand of conditional execution, the Creg module is added to export the zero signals to ALUs and speed up the operations. Besides, we simplify the clock tree and decrease the delay time and skew of it. Also, low-voltage and low-power technology is used. The simulation result shows that the decode cell is optimized by 16% in area and 20% in delay. The BYPASS data-select module results in reduction of 11.3% in area and 13.2% in delay. Register file's power is lower by 3.5% and area smaller by 14.2%.2. We fulfill the full-custom design of a 0.13μm CMOS high-reliability 16×32-bit 10-read, 6-write register file and build the timing model for it. With the purpose of high reliability, we implement the design with complementary CMOS and pass-transistor logic without low-voltage involved. Suppoting"single-step debug"of the whole chip, we implement data access to register file for ET. By simulation and verification, the register file can work at the frequency of 300MHz under the Worst condition with IR Drop accounting for 1.67% of VDD.3. We propose ciucuit migration flow based on SKILL scripts. Morely, layout migration is implemented using Laker tool. By means mentioned above, the design of a 0.13μm high-reliability 10-read, 6-write register file is migrated from 0.13μm to 90nm.4. We present verification of register file. Combining NC-Verilog with SpiceTime tools, we rebuild the function model of register file on gate-level hiberarchy. We also exploit a new set of testbench which covers 100% of its function of"multi read and multi write".