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Full Custom Design And Implementation Of High-Speed Register File In X Processor

Posted on:2010-10-14Degree:MasterType:Thesis
Country:ChinaCandidate:H H WangFull Text:PDF
GTID:2178360278956799Subject:Software engineering
Abstract/Summary:PDF Full Text Request
An important factor preventing the accessing speed of the microprocessor from improving is the "memory wall", and the performances of the register files being located in the key path of data are most serious in recent years. The X microprocessor is a 64-bit multicore multithreading high-performance microprocessor, and it's Integer Register File which is the key point in the design needs high frequency, large scale and mult-port. Considering the result of half-custom design based on standard cell is hard to satisfy the requests, the full-custom design method is needed. The full-custom design and implementation of the high-speed register file has important research signification and engineering practicality to the independent development of CPU .The 3-read, 2-write ports, 128-word×72-bit, supporting multi-theading Integer Register File is implemented in 0.13μm CMOS process. The typical simulation result of layout indicates: the read delay is less than 700ps, and the write delay is less than 570ps. Comparing with the synthesis result of half-costom design based on standard cell, the accessing time reduced from 1.05ns to less than 700ps, which is optimized nearly 33%, and the area reduced from 598793μm~2 to less than 455600μm~2, which is optimized nearly 24%. They both achieve the design aim.The thesis mostly aim at high speed and also congsider the reliability, area and etc. factors.Combining with theoretical analyzing and simulation comparing, it optimizes the chief factors which affect the Register File's speed.1) Combining with the RF's characteristic of supporting multi-threading , it adopts the strategy of judging and selecting after the 4-threading's reading out parallel which reduces the delay of the key path effectively;2) It designs an improved dynamic domino decoder which has almost 12% advance of the speed to the normal domino decoder;3) Using the technic of reinforcing the charge in the key path to accelerate the speed 10%~20%, such as the decoer and the read-select circuit.
Keywords/Search Tags:Register File, Multi-Threading, Full-custom Design, High-Speed Circuit Design
PDF Full Text Request
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