Research And Implementation For PCIE SSD In High Performance Application

With the advent of the era of big data, the storage demand of enterprise and user isgrowing rapidly. Data has become a company’s core resources, and therefore put ahigher demand on the safety and reliability of the data storage. These technologies,including software and hardware, have prompt the development of storage technology,and impact the traditional storage architecture greatly, which provides a broad space forrelated research.In order to meet the application requirements of data-intensive mass storage system,and improve the bandwidth of the storage system, SSD based on the PCIe interface hasbeen developed. We designed and implemented a layered driver for our PCIe SSDdevices independently developed. Through the cooperation of the layered drivers, thePCIe SSD has been correctly mounted on the system, and improved the bandwidth andspace utilization. The main works accomplished in this thesis are as following:1) PCIe SSD driver design for Windows, including the study on storage stack ofWindows operating system and the WDM driver framework working mechanism. Wedesigned a layered driver, the upper driver registered the hardware as a disk device inthe Windows operating system, taking a different IO path with traditional drive in orderto reduce the overhead of protocol conversion; the lower driver used request queue,TAG registers to handle out-of-order requests. The two layers collaborate to improvesystem performance.2) FTL design for large scale NAND Flash, and a process-based block allocationstrategy. Experimental results show: the FTL can effectively utilize the large memoryspace on host, process-based block allocation strategy can more effectively manage theflash to improve garbage collection efficiency and performance of the flash drive layer.3) import a write buffer in the driver layer. This is an effective solution to thecontradictions of different granularity between file system and devices, which reducesthe number of flash memory erase operation, improve the response speed and efficiencyof garbage collection performance.4) The mechanism of the high-speed transmission is studied, with a request queueand TAG register to handle concurrent requests for out-of-order requests. Take fulladvantage of the high-speed bandwidth of the PCIe interface, and reduce the number ofinterrupts, and make the request to get the correct response in case of out-of-orderprocessing.