Research On High Speed Data Transmission System Technology Based On PCIe

In recent years,with the rapid development of high-speed data transmission technology,the massive data transmitted by various devices is growing exponentially.On this basis,in order to improve the efficiency of data processing,hardware acceleration technology has also been a good development.To transmit a large amount of data to the host and hardware board stably and efficiently,and carry out subsequent processing is extremely important.Based on this background,this paper mainly studies the following contentsThis paper analyzes and studies the protocol specification of the high-speed serial bus,the function of the transaction layer and the data packet structure of the transaction layer.By studying the topology of the PCIe bus,the architecture of the transmission system is determined,which lays the foundation for the subsequent design of the PCIe data transmission system.This paper studies the user interface timing of Xilinx 7 Series FPGA PCIe IP core,and completes the design of PIO and Bus Master DMA.This paper verifies the two types of transmission mode of the PCIe,and analyzes the existing problems,which provides a design idea for the design of high-speed data transmission of the PCIe with XDMA.This paper studies the implementation method of Scatter-Gathered DMA high-speed data transmission design based on XDMA IP core,and completes the design of XDMA hard core user timing interface and transmission logic.Through the joint debugging of driver and board,it completes the test and verification of high-speed data transmission design of PCIe based on XDMA on the hardware development platform.On this basis,this paper proposes a transmission architecture based on XDMA IP core,and designs the corresponding host computer program for it.The architecture can buffer the data of receiving host computer program,realize the communication between host computer and FPGA board,process the data in the board at the same time,and finally send the processed data back to the host computer program for subsequent data processing.The transmission architecture provides a feasible idea for the hardware acceleration architecture of gateway station in satellite communication.