Research Of High Speed Data Transmission Technology Based On PCIe Bus

Computer technology and high-speed data acquisition technology have developed rapidly in recent years,and the massive data gathered by various kinds of information is growing in an exponential manner.Especially in the field of radar imaging,high-resolution SAR image data is constantly increasing,it is extremely important how to stably and efficiently transfer these huge data volumes to the host device for subsequent image processing.The PCIe bus is widely used in high-speed data acquisition systems because of its advantages,e.g.high transmission bandwidth and highly scalable functions.Based on this background,the following contents are studied in this article:1?The PCIe high-speed serial bus protocol specification is deeply studied,especially the function and the structure of the transaction layer are studied and analyzed in detail.Through the study of the PCIe bus topology,the process of data transmission between the host,the endpoint,the switch and the root complex is clarified,and the key role played by the upper computer and the driver is also deeply understood,which lays a theoretical foundation for the subsequent design of PCIe data transmission based on Xilinx IP core.2?In this paper,the user interface timing of Xilinx K7 FPGA PCIe hard core is studied.Based on this,the traditional TRN transaction interface is used as the user interface,and the bus master DMA controller is designed.The design simplifies the state transition process of the sending engine state machine and the receiving engine state machine,and adds the asynchronous FIFO data transmission channel for the sending and the receiving transaction interface respectively,which solves the problem of cross clock processing when data transfer between other modules in the FPGA and the DMA controller.Finally,the TRN-to-AXI bridge logic is designed and realizes the interface timing conversion between the DMA controller and the PCIe hard core.All of these provide a feasible design idea for the further design of DMA transmission by using PCIe hard core.3?The implementation method of DMA high speed data transmission based on the Xilinx V7 FPGA XDMA hard core is studied.The design of data transmission logic for user interface of the XDMA hard core is completed.The construction of the DMA reading and writing simulation platform based on Root Port Model is also studied,which provides a simulation verification method for the related logic design.Eventually,through the close cooperation between the host computer and the driver,the test and verification of the PCIe3.0 transmission design based on XDMA hard core are completed on the VC709 hardware development platform.The test result shows that when the single DMA transmission packet is set to 8MB,the effective data bandwidth of the DMA read transmission can reach 3.87GB/s,and the effective data bandwidth of the DMA write transmission can reach 4.16GB/s.It can satisfy the requirement of most data acquisition system for high speed data transmission.