Design And Implementation Of High-Speed Data Transmission System With PCIe Bus Base On FPGA Architecture

PCI Express(PCIe) bus interface as a new generation,has been widely applied after releasing. It have effectively solved the problem that the data throughput in High-speed data transmission system, was widely applied to the field of radar, satellite,measurement and so on. Due to the complexity of the protocol, in fact the company that had researched and Developed the PCIe chip was very few. Many IC designers choice a dedicated PCIe chip as solution, in contrast, losing the flexibility of the protocol.In this thesis, Adopting Altera’s Stratix IV family EP4SGX230KF40I4 as control chip, design and implementation a high-speed data transmission system, which is base on FPGA and PCI X4 architecture.The design ensures the greater transmission at bandwidth, and also can modify the configure of PCIe’s hardcore to meet the demand,effectively promotion the operating range of PCIe. The main contents of the thesis as follows:1)the thesis study on the PCIe protocol and give a simple introduction about protocol layers, introduce the three type of PCIe’s routing and PCIe device’s space configure.2)Hardware system is implemented by Qsys design procedure,which includes these modules like PCI Express、SGDMA and Chip Memory and so on. The hardcore of PCIe is realized PCI Express1.0 protocol, the soft core of SGDMA implements the hardware basis of scatter/gather DMA(Direct Memory Access).Testing the system performance about the speed of DMA reading and writing, and the parameter of the system use for improving the system’s performance.Finally, having introduced the hardware logic and register in hardware system of the actual project.3)Having developed the driver which is matched the hardware system described by above chapter. The driver is developed on Windows system and Kylin operating system which is used the Linux Kernel 3.10.52. The thesis detail of the techniques and mechanisms used in the driver structure, and the design of interrupt structure is the innovation and the focus of this article.By the basis of the interrupt structure and SGDMA hardware logic,the driver achieve that multiple channels launch DMA task concurrently.Therefore, it effectively improves the overall throughput of system.4)According to user needs,the operation of accessing the hardware is packaged as afunction interface. Designed the corresponding dynamic link library which include all function interface.In this way, the user will safe operate the hardware device and improving the stability of operating system.5)Using GUI program to test the performance of the system. The program was developed by MFC(Microsoft Foundation Classes) On the Windows system and Qt software On the Kylin system.Testing each channel data throughput on the mode of data FIFO(First In First Out) queue half-full interrupt and timer interrupt.The test results show that the system can satisfy actual engineering needs, and can be applied to practical engineering.