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Design And Implemention Of A High Speed Data Transmission System Based On PCIE

Posted on:2017-02-15Degree:MasterType:Thesis
Country:ChinaCandidate:W L LiFull Text:PDF
GTID:2308330485985042Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
With the development of communication technology, modern communication system requires increasingly large data bandwidth. This correspondingly puts forward higher requirement for data transmission system. The PCIE(PCI Express) bus, as the third generation data bus, has been devices sensitive-speedin usedwidely, such as high-speed data acquisition plate, server, workstation and so on.We proposes thatsystemion transmissdata speed-high a based on PCIE bus. To meet the requirement of the project, our system uses two high-speed, 4-channel ADC sampling plate as data sample equipment, so it supports up to 8-channel sampling. It has500 MSps sampling rate when works at 8-channel sampling, and supports 5GSps sampling rate when single channel. Two high-speed ADC sampling plate connect with two Xilinx-ML605 evaluation board respectively by the FMC interface. To achieve the8 channel synchronous sampling, we distinguish the two ML605 as main device and slave device. The main device transmits the signal of start sampling to slave device.From this way, we can achieve 8 channel synchronous sampling. When FPGA achieves the start sampling signal, the sampling data firstly are transmitted to DDR3 in the ML605 by the memory controller in FPGA. When the DDR3 is full, the logic modules in FPGA take out the data in DDR3, and transmit it by way of DMA to host computer from the PCIE bus. The PCIE interface is implemented by the hard PCIE IP core in V6 FPGA that on the ML605 evolution board, and the DMA logic is design by the Verilog language. To improve the data transmission efficiency, our system sets the PCIE to PCIE2.0 with 4 channel. So the maximum bandwidth of our PCIE system is 2GB/s. We design the DMA size to 4MB, and this value is the best result from a mass of test.The test result indicates that the DMA operates at a high efficiency, and the speed of toup runsion transmissdata 1.78GB/s, which close to the theoretical PCIE speed.But device, storage ofimpact theof because hardware, and softwarehost the actual transfer rate is very low. The actual speed of DMA is about 500MB/s. Our systemion transmissdata speed-high is stable and accurate, and it can meet the requirements of the project.
Keywords/Search Tags:high-speed ADC sampling, FPGA, PCIE, DMA
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