Research On High-speed Transmission Technology Based On PowerPC

With the rapid development of high-performance embedded system interconnection technology,the development of agile and continuous integration era,software systems and hardware systems are becoming more and more intelligent,and the data transmission performance of embedded systems is getting higher and higher.While the amount of information is increasing,the system's large-capacity real-time data processing capability becomes the key of system performance,and high-speed data transmission is the basis of real-time data processing.Embedded high-speed data transmission system is mainly used in the field of industrial control,national defense science and technology,which not only need to ensure the integrity of the system transmission data and reliability,but also the system to meet the modular,miniaturization and lightweight requirements.Choosing the appropriate embedded processor system architecture,choosing the appropriate data transmission bus,designing the embedded system to meet the high speed data transmission is the popular research and the design difficulty and the key.In this paper,high-speed serial PCIE bus protocol and Rapid IO bus protocol based on the establishment of high-speed data transmission interconnection system,PCIE bus and Rapid IO bus ideal transmission rate of more than 10 Gbps,Is the embedded interconnection system is basically used directly or indirectly use the bus way to achieve high-speed data transmission function.The main contents and work of this paper are as follows: 1)In view of the high-speed data transmission in high-speed and large-capacity storage arrays,the inter-board PCIE bus and Rapid IO bus transmission technology are studied,and the high-speed serial bus transmission characteristics are fully utilized to improve the overall data transmission performance.2)A high-speed data transmission system based on Power PC architecture P2020 E processor is designed for high-speed transmission system.The PCIE bus is designed with the Rapid IO bus interface,and the U-Boot program,embedded Linux kernel and system running Root file system.3)For the DMA controller features in the P2020 E processor,the PCIE bus driver and the Rapid IO bus driver use the asynchronous DMA transfer mode to solve the memory frequent mapping operation in the synchronous DMA transmission mode.In the open MMU mechanism at the same time,the use of consistent memory mapping,to solve the streaming mapping mode memory access and cache data inconsistencies,reduce the CPU to read and write memory operations.Use the ring DMA cache in the Rapid IO driver and optimize the global shared memory of the DMA buffer.4)For the interrupt system processing features,in the driver,PCIE bus driver using MSI interrupt mechanism,Rapid IO bus using Message messaging mode.In user space,I/O transactions that need to operate PCIE devices and Rapid IO devices are done through asynchronous I/O,which waits for synchronization during I/O polling operations,and does not require CPU resources to be associated I/O tasks.5)Optimize the implementation of the PCIE device driver and Rapid IO device driver,respectively,the corresponding device driver for the actual data transmission test,according to the test results have been optimized after the performance of the device driver,and according to the test structure and theoretical transmission Bandwidth comparison,analysis of the reasons for the gap,and finally look forward to the PCIE bus interface and Rapid IO bus interface,the future direction of development.