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Exact Timing Modeling Techniques For Full-custom Research And Design

Posted on:2014-02-02Degree:MasterType:Thesis
Country:ChinaCandidate:M M DongFull Text:PDF
GTID:2268330422473821Subject:Software engineering
Abstract/Summary:PDF Full Text Request
With the improvement of integrated circuit, high performance processor designusing semi-custom/full-custom design. During semi-custom/full-custom design flowfull-custom non-standard units need to be established appropriate timing models.Full-custom module timing modeling mainly rely on semi-automatic process, whichdepends on manual analysis of the circuit path for various timing path. This is not onlytime-consuming, but also the LIB file is not reliable. We discuss how to accurately andquickly complete timing modeling in deep sub-micron process based on the knowledgeof detail study of timing modeling system and method. The main work and researchresult of this paper including:Designed a method to achieve full-custom macro module based on dichotomyand named the tool DICHO. DICHO includes three parts: constraints_arcmodeling, delay_arc modeling and power modeling. The constraint_arcmodeling mainly reflected the idea of dichotomy, first find the suitable intervalvalue for dichotomy, and then find value through dichotomy in the range; thedelay arc modeling using dynamic simulation, automatic measurement delay;power values are got from dynamic simulation too. The method just needsimply random waveforms, modify the configuration file to extraction moduletiming model.In order to ensure the accuracy of the timing library data, this paper presents amethod for library timing verification and named it LIB_Veri. First LIB_Verineed loaded simulate files into simulation environment, then check thesimulation result. If result is right, ok; or this program will modify the value inlibrary file.The YHFT_DX processor and FT_QX processor both are high-performancemicroprocessor, using semi-custom/full-custom design. DICHO complete timemodeling and LIB_Veri complete verification of the full custom modules ofYHFT_DX and FT_QX microprocessor, including: two register files and fivememory modules.The above research greatly reduces the complexity of timing modeling work fromtiming modeling to timing verification, avoid human error, improve the efficiency andaccuracy of the timing modeling. Achieved well results in practical engineeringapplications.
Keywords/Search Tags:Timing Model, Dichotomy, Constraint_Arc, Delay_Arc, LIB-Verification
PDF Full Text Request
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