Automation Achieved Of Function Verification And LIB Extraction For IP Core

To enable fast turn-around time for modern integrated circuits(ICs), it is widely used in the field to combine fully custom and semi-custom design approaches. For an IP core with a large number of ports and logic circuits, its functional verification and timing analysis usually account for the major part of the design cycle. During this time, it is one of the most tedious and time consuming tasks to write the analysis result of the timing and power into the LIB file with the correct format.This paper studies the functional verification method, timing modeling principles and timing model analysis for IP cores. We found that, with the existing methods, both functional verification and the timing analysis need excessive manual intervention by the validator due to the inaccuracy of the existing error position locating feature in the EDA tools. In this paper, we explained our own scripts to enable automatic functional verification and timing analysis. Our scripts can accurately locate the position in the circuit that results in the differences between the SPICE simulation and RTL simulation results, and time of when the differences are shown, simplifying the work of function verification. Compared to manual analysis of analog waveform authentication method, our method is more efficient and less error-prone. At the same time, this is a get-around for the faulty error-locating feature of the EDA tools. Compared to traditional LIB extraction methods, the method proposed in this paper does not require the analysis of the circuit design, layout and look for the critical timing paths of each input pin, and only need the circuit netlist file, where the efficiency and accuracy has been greatly improved.The correct functionality of the method is verified by comparing the extracted LIB files and extracting time for a memory and register files. The results show that, compared to waveform of artificial methods, the automation tool designed for functional verification compared with currently available methods improved by 70% in the run time. Compared with the analysis path, lay on the label analog layout, LIB automated extraction tools increased by nearly 38% on the running speed.