Design Of A12-bit Ultra-low Power CMOS DAC Using The Combination Of Current Steering And Resistive Divider

Digital-to-Analog Converters (DAC) using mobile and portable devices had an extremelylow-power requirement. The CMOS process has a natural advantage of lowering the dynamiccurrent dissipations and the costs, so the CMOS process is a good choice for implementation oflow power DAC mentioned above. For these reasons, low-power CMOS DACs play animportant role in these fields.This paper presents the design of an ultra-low power DAC. The segmented architecture withthe current-steering and the resistive-divider was proposed by discussing a number of low powerDACs reported in latest Journals. The proposed architecture used the unit current steering as the6-bit MSB DAC and used the resistive divider as the6-bit LSB DAC. A high performancebandgap reference was integrated in the proposed DAC. The reference had high orders ofcurvature-compensation by using MOS transistors operating in weak inversion region. An outputoperational amplifier using slew-rate enhancement was applied to improve the conversion rate ofthe DAC. The amplifier used a class AB common source stage as an output stage.The mechanisms of the DAC, the reference and the amplifier were analyzed thoroughly andthe corresponding circuits were implemented in the1.8-V2P6M CMOS0.18um technology. Theexperimental results show that the DAC only consume1mA at1.3V while the conversion rate is20MHz. The measured single-tone SFDR is up to60dBFS at1-MHz output frequency. Thereference achieves3.4ppm/°C over the temperature range of-40°C to120°C at1.2V supplyvoltage. In addition, it achieves linear regulation performance of0.10%/V.