Research And Design Of 14-bit Segmented Current Steering DAC

With the rapid development of computer processing technology,the requirements for speed and resolution of digital processor is increasing whether in civil or military fields.At the same time,with the development of integrated circuit technology becoming more and more mature,which makes it possible to develop high-speed and high-resolution data processor.Digital-to-analog converter is one of the key interfaces between digital signal and analog signal,its speed and resolution have become the bottleneck of modern communication and data processing.Therefore,it is of great significance to study high-speed and high-resolution DAC.A 14-bits segment current-steering DAC is designed based on the TSMC 40 nm CMOS process.The circuit adopts fully differential output and dual power supply.The analog and digital power supply voltages are 1.8V and 1.1V respectively.The schematic design and layout design of the key modules of DAC are completed,including band-gap reference voltage source,voltage-to-current,bias circuit,current source array,switch array,latch,segment decoding circuit,input register and clock driver circuit and the chip test scheme is given.In order to compromise the influence of circuit area,performance and complexity,DAC is divided into5+4+5 three-segment decoding structure,which combines the advantages of binary decoding and thermometer decoding to achieve better static performance.The band-gap reference voltage source adopts low voltage structure,which realizes the function of adjustable temperature coefficient and output voltage swing.The latch adopts a limiting structure to reduce the swing of the output control signal and make its crossing point below the threshold voltage,so as to ensure the stable operation of the current source array and reduce the clock feed-through effect of the switch tube.The current source array adopts cascode structure,which ensures a larger output impedance of the current source,it improves the matching characteristics of the current source and the dynamic performance of the DAC.Based on the mismatch analysis of the current source,the minimum size of the current source was determined.In the layout of current source array,the high current sources are split and arranged to a symmetrical position in space to reduce the systematic error based on the common center four-quadrant symmetric method.The post-simulation results show that the DNL and INL of the DAC are 0.30 LSB and0.38 LSB when the clock frequency is 500 MHz,the power consumption is 17.99 mW,the SFDR is 94.66 dB when the sinusoidal input signal frequency is 5.86 MHz,and the SFDR is 78.81 dB when the input frequency is 130.68 MHz.At 1GHz clock frequency,the DNL and INL of the DAC are 0.47 LSB and 0.57 LSB,and the post-simulated SFDR is 89.99 dB at the input frequency of 11.72 MHz.