A Design Of Segmented Current-Steering Digital-to-Analog Converter

With both the advancement of the IC process and the development of IC technology in communication area, the frequency of microprocessor and wireless communication device has become much higher, which adds stricter requirement on the transfer and conversion of the mixed signal. As a result, how to design a high speed and high resolution digital-to-analog converter has become a new challenge. According to this requirement, this thesis researches and designs a high speed and high resolution Digital-to-Analog Converter.Firstly, on the basis of theoretical analysis and circuit design, the thesis researches two major blocks, Digital-to-Analog Converter and Bandgap Reference Circuit. After comparing two types of circuit structures, combined with the specification, the segmented current-steering DAC circuit is chosen. Based on the consideration of the chip area, the complexity of the circuit and so on, the design adopts 5+4+5 segmented structure to achieve the optimum of unit current source and binary weighted current source. Besides, it discusses the key factors which influence the DAC's performance on both aspects of circuit and layout.Secondly, this thesis discusses some aspects related to the DAC such as pre-simulation, layout, DRC/LVS and post-simulation. The simulation of DAC is implemented in 0.35μm CMOS process using Cadence ADE, and its results demonstrate that the DNL is±2.0LSB, INL is±3.5LSB, and SFDR=78.2dB @ fdata=130MSPS, fout=24.6MHz in the DAC.At last, conclusions on the research work discussed above have been given at the end of the thesis and perspective research based on this thesis has also been put foward.