Analytic Calculation Of Jitter At LPDDR4 I/O Interface

With the development of mobile memory chips toward high speed,low power consumption,and high density,the power supply noise in high-speed digital circuits inside the chip is becoming more and more serious.The impact of power supply noise on the internal clock reference and signal timing margin is extremely prominent.The operating voltage of the low-power memory is greatly reduced,making the I/O interface more sensitive to power noise.Power supply induced jitter(PSIJ)has become one of the major bottlenecks in designing I/O interfaces.Therefore,this article focuses on the jitter caused by power supply noise in the LPDDR4 memory interface.In this paper,the architecture and main characteristics of the interface,the causes of power noise and its impact on the interface link are elaborated.The equivalent model of each specific unit of the interface is mainly established,and the transmission functions of jitter induced by power supply noise are derived based on the equivalent model.The work results are summarized as follows:(1)For the new driver structure,termination logic and packaging of the LPDDR4 I/O interface,analyze their specific structures and establish equivalent models.This article details the structure and physical characteristics of LPDDR4 interface,and establishes a reasonable equivalent model for the driver and termination logic.Then,for the complex interconnection path from the memory driver to the processor receiver,according to the specific structures of the WLP package,each basic unit of the I/O interconnection is analyzed in detail,and the electrical lumped modeling is performed.(2)The causes of power supply noise and its impact on the interface link are introduced.This paper describes the composition of the power distribution network,introduces the components of the power distribution network,analyzes its characteristics,and studies the generation mechanism and main types of power noise.The simultaneous switching noise has a significant impact on jitter and the entire high-speed system with low operating voltage.Thereafter it describes the effect of power supply noises on driver output signals.(3)This article proposes a numerical calculation method for jitter induced by power supply noise based on the established LPDDR4 I/O interface model.After analysis,it is found that power noise and ground noise has completely different effects on the interface output signal.This paper analyzes the specific reasons for power noise and ground noise affecting I/O interface,and verifies the correctness of this conclusion through simulation eye diagrams.Then,in the simulation software,the timing interval error(TIE)and jitter transfer function induced by ground noise are verified and analyzed in the frequency domain,and the accuracy of the estimation value of jitter is compared with professional simulation results.